A 0.7V 1.6mW fractional-N synthesizers for BLE RF transceiver in 40nm CMOS

This paper presents a low-power fractional-N synthesizer for BLE with gate-switching charge pump (CP) and high-speed prescaler. To reduce the current mismatch under low supply voltage, master-slave rail-to-rail operational trans-conductance amplifier (OTA) structure is employed to CP; Current self-matching technique guarantees charging equal discharging current. The embedded logic gates power switch are true-single-phase-clock (TSPC) consumption improve operating speed of divider. Random dither injected into ΔΣ modulator prolong period output sequence. proposed phase-locked loop (PLL) implemented in 40-nm CMOS process. It achieves -85.94dBc/Hz@100kHz -109.18dBc/Hz@1MHz mode while consuming 1.6mW 0.7V voltage supply.